mirror of https://github.com/zachjs/sv2v.git
39 lines
1.1 KiB
Haskell
39 lines
1.1 KiB
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Verilog-2005 forbids block declarations with default values. We convert
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- these assignments to separate statements. If we handle static lifetimes in
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- the future, this conversion may have to change.
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-}
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module Convert.BlockDecl (convert) where
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import Data.Maybe (mapMaybe)
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import Convert.Traverse
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import Language.SystemVerilog.AST
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convert :: [AST] -> [AST]
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convert =
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map
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$ traverseDescriptions $ traverseModuleItems
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$ traverseStmts $ convertStmt
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convertStmt :: Stmt -> Stmt
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convertStmt (Block name decls stmts) =
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Block name decls' stmts'
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where
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splitDecls = map splitDecl decls
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decls' = map fst splitDecls
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asgns = map asgnStmt $ mapMaybe snd splitDecls
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stmts' = asgns ++ stmts
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convertStmt other = other
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splitDecl :: Decl -> (Decl, Maybe (LHS, Expr))
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splitDecl (Variable d t ident a (Just e)) =
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(Variable d t ident a Nothing, Just (LHSIdent ident, e))
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splitDecl other = (other, Nothing)
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asgnStmt :: (LHS, Expr) -> Stmt
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asgnStmt = uncurry $ AsgnBlk AsgnOpEq
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