mirror of https://github.com/zachjs/sv2v.git
71 lines
2.1 KiB
Systemverilog
71 lines
2.1 KiB
Systemverilog
module top;
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reg input_a, input_b, input_c;
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wire output_and, output_and_delay;
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wire output_not, output_buf_delay;
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and (output_and, input_a, input_b);
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and #1 (output_and_delay, input_a, input_b);
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not (output_not, input_a);
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buf #2 foo_name (output_buf_delay, input_a);
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wire output_bufif0_delay, output_bufif1_delay;
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wire output_notif0_delay, output_notif1_delay;
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bufif0 (output_bufif0_delay, input_a, input_b);
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bufif1 (output_bufif1_delay, input_a, input_b);
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notif0 (output_notif0_delay, input_a, input_b);
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notif1 (output_notif1_delay, input_a, input_b);
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wire output_cmos, output_rcmos;
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cmos (output_cmos, input_a, input_b, input_c);
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rcmos (output_rcmos, input_a, input_b, input_c);
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wire output_nmos, output_pmos;
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wire output_rnmos, output_rpmos;
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nmos (output_nmos, input_a, input_b);
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pmos (output_pmos, input_a, input_b);
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rnmos (output_rnmos, input_a, input_b);
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rpmos (output_rpmos, input_a, input_b);
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wire output_nand, output_or, output_nor, output_xor, output_xnor;
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nand (output_nand, input_a, input_b);
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or (output_or, input_a, input_b);
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nor (output_nor, input_a, input_b);
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xor (output_xor, input_a, input_b);
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xnor (output_xnor, input_a, input_b);
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initial repeat(2) begin
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$monitor("%3d ", $time,
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input_a, input_b,
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output_and, output_and_delay,
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output_not, output_buf_delay,
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output_bufif0_delay, output_bufif1_delay,
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output_notif0_delay, output_notif1_delay,
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output_cmos, output_rcmos,
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output_nmos, output_pmos,
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output_rnmos, output_rpmos,
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output_nand, output_or, output_nor, output_xor, output_xnor);
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#1;
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#1; input_a = 1;
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#1; input_c = 0;
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#1; input_b = 0;
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#1; input_b = 1;
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#1; input_c = 1;
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#1;
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#1; input_a = 0;
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#1; input_b = 0;
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#1; input_a = 0;
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#1; input_b = 1;
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#1; input_c = 0;
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#1; input_a = 1;
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#1; input_b = 0;
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#1; input_c = 1;
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#1; input_a = 1;
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#1; input_b = 1;
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#1;
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#1;
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#1;
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end
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endmodule
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