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Zachary Snow
661703a8c2
- fix wildcard imports shadowing other items - fix explicit imports depending on other items - fix example export in package.sv
6 lines
96 B
Verilog
6 lines
96 B
Verilog
module top;
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localparam P_X = 10;
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localparam Y = P_X;
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initial $display(Y);
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endmodule
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