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Zachary Snow
9a38225b1d
- entirely new PackedArray conversion (always flattens) - typedef and struct correctly order packed ranges when combining types - Stmt LHS traversal no longer traverses nested statements to avoid double conversion - Logic conversion applies to `initial` blocks` - new and modified tests to cover these cases
4 lines
45 B
Verilog
4 lines
45 B
Verilog
module top;
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Example example();
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endmodule
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