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Zachary Snow
8d37db30e5
- modports can use complex expressions - update interface_infer test for consistency across simulators - fix interface inlining of implicitly typed data declarations
19 lines
319 B
Verilog
19 lines
319 B
Verilog
module top;
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reg clock;
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initial begin
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clock = 1;
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forever #5 clock = ~clock;
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end
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initial begin
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repeat(30)
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@(posedge clock);
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$finish;
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end
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Tester #(1) t1(clock);
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Tester #(2) t2(clock);
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Tester #(3) t3(clock);
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Tester #(4) t4(clock);
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endmodule
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