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Zachary Snow
2a2d819baa
- assertions, gen case, and inout - simplify block codegen - remove blank lines in tasks with no inputs
18 lines
266 B
Verilog
18 lines
266 B
Verilog
module top;
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reg clock;
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initial begin
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clock = 0;
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repeat (100)
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#1 clock = ~clock;
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end
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reg clear;
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initial clear = 0;
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reg data;
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initial data = 0;
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Module m(clock, clear, data);
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initial m.hello;
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endmodule
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