mirror of https://github.com/zachjs/sv2v.git
55 lines
1.7 KiB
Haskell
55 lines
1.7 KiB
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Verilog-2005 requires that all functions have at least one input port.
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- SystemVerilog allows functions to have no arguments. This conversion adds a
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- dummy argument to such functions.
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-}
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module Convert.EmptyArgs (convert) where
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import Control.Monad.Writer
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import qualified Data.Set as Set
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import Convert.Traverse
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import Language.SystemVerilog.AST
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type Idents = Set.Set Identifier
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convert :: [AST] -> [AST]
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convert = map $ traverseDescriptions convertDescription
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convertDescription :: Description -> Description
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convertDescription (description @ Part{}) =
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traverseModuleItems
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(traverseExprs $ traverseNestedExprs $ convertExpr functions)
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description'
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where
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(description', functions) =
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runWriter $ traverseModuleItemsM traverseFunctionsM description
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convertDescription other = other
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traverseFunctionsM :: ModuleItem -> Writer Idents ModuleItem
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traverseFunctionsM (MIPackageItem (Function ml t f decls stmts)) = do
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let dummyDecl = Variable Input (Implicit Unspecified []) "_sv2v_unused" [] Nothing
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decls' <- do
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if any isInput decls
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then return decls
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else do
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tell $ Set.singleton f
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return $ dummyDecl : decls
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return $ MIPackageItem $ Function ml t f decls' stmts
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where
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isInput :: Decl -> Bool
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isInput (Variable Input _ _ _ _) = True
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isInput _ = False
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traverseFunctionsM other = return other
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convertExpr :: Idents -> Expr -> Expr
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convertExpr functions (Call (Ident func) (Args [] [])) =
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Call (Ident func) (Args args [])
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where args = if Set.member func functions
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then [Just $ Number "0"]
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else []
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convertExpr _ other = other
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