mirror of https://github.com/zachjs/sv2v.git
40 lines
1.2 KiB
Haskell
40 lines
1.2 KiB
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for unnamed blocks with contain data declarations
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-
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- SystemVerilog allows data declarations to appear in all blocks, but Verilog
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- allows them to appear only in blocks that are named. This conversion gives
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- such blocks a unique name to placate strict Verilog frontends.
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-}
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module Convert.NamedBlock (convert) where
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import Control.Monad.State.Strict
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import Convert.Traverse
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import Language.SystemVerilog.AST
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convert :: [AST] -> [AST]
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convert = map $ traverseDescriptions convertDescription
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convertDescription :: Description -> Description
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convertDescription description =
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evalState (traverseModuleItemsM traverseModuleItem description) 1
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where
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traverseModuleItem = traverseStmtsM $ traverseNestedStmtsM traverseStmtM
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traverseStmtM :: Stmt -> State Int Stmt
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traverseStmtM (Block kw "" [] stmts) =
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return $ Block kw "" [] stmts
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traverseStmtM (Block kw "" decls stmts) = do
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x <- uniqueBlockName
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return $ Block kw x decls stmts
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traverseStmtM other = return other
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uniqueBlockName :: State Int String
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uniqueBlockName = do
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cnt <- get
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put $ cnt + 1
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return $ "sv2v_autoblock_" ++ show cnt
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