mirror of https://github.com/zachjs/sv2v.git
13 lines
346 B
Systemverilog
13 lines
346 B
Systemverilog
// pattern: inlining instance "mod" of module "Module" would make expression "x" used in "mod" resolvable when it wasn't previously
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// location: interface_bad_expr_module.sv:6:5
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interface Interface;
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endinterface
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module Module(Interface i);
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assign x = 1;
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endmodule
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module top;
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wire x;
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Interface intf();
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Module mod(intf);
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endmodule
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