mirror of https://github.com/zachjs/sv2v.git
25 lines
593 B
Systemverilog
25 lines
593 B
Systemverilog
module top;
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typedef struct packed {
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logic [1:0][1:0][1:0] x;
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} U;
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typedef union packed {
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logic [$bits(U) - 1:0][7:0] a;
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logic [3:0][15:0] b;
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U [7:0] c;
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} T;
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typedef struct packed {
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logic [$bits(U) - 1:0][7:0] a;
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logic [3:0][15:0] b;
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U [7:0] c;
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T [2:0] d;
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} S;
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if ($bits(U) != 8)
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$error("invalid width U");
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if ($bits(T) != 64)
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$error("invalid width T");
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if ($bits(S) != 64 * 6)
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$error("invalid width S");
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logic [31:0] x;
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assign x[$bits(U) - 1:0] = '1;
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endmodule
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