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module mod(inp, out);
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parameter COUNT = 1;
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input wire [COUNT * 3 - 1:0] inp;
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output reg [COUNT - 1:0] out;
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genvar i;
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generate
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for (i = 0; i < COUNT; i = i + 1)
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always @*
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if (inp[i * 3] | inp[i * 3 + 1])
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out[i] = inp[i * 3 + 2] ^ inp[i * 3 + 1];
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endgenerate
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endmodule
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