mirror of https://github.com/zachjs/sv2v.git
17 lines
456 B
Systemverilog
17 lines
456 B
Systemverilog
module mod(inp, out);
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parameter COUNT = 4;
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typedef struct packed {
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logic a, b, c;
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} struct_t;
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typedef union packed {
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logic [2:0] raw;
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struct_t fields;
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} union_t;
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input union_t [COUNT - 1:0] inp;
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output logic [COUNT - 1:0] out;
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for (genvar i = 0; i < COUNT; i += 1)
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always_comb
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if ((inp[i].raw & 3'b011) != '0)
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out[i] = inp[i].fields.a ^ inp[i].fields.b;
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endmodule
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