mirror of https://github.com/zachjs/sv2v.git
21 lines
734 B
Verilog
21 lines
734 B
Verilog
module top;
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genvar i, j, k;
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generate
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for (i = 1; i <= 8; i = i * 2) begin : blk
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for (j = 0; j < 4; j = j + 1) begin : blk
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wire [i - 1:0] x;
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assign x = i;
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initial $display("intf %b", x);
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end
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for (j = 0; j < 4; j = j + 1) begin : alt
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for (k = 0; k < 2; k = k + 1)
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initial $display("foo %0d", k);
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initial $display("mod [%0d] %b", j, top.blk[i].blk[j].x);
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initial $display("mod shadowed_intf %0d %b", j, top.blk[i].blk[j].x);
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end
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for (k = 0; k < 2; k = k + 1)
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initial $display("bar %0d", k);
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end
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endgenerate
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endmodule
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