mirror of https://github.com/zachjs/sv2v.git
28 lines
667 B
Systemverilog
28 lines
667 B
Systemverilog
module mod(
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input logic clk,
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input byte row, col,
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output logic [47:0] flat
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);
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typedef byte T [2][3];
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function automatic T f;
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input T inp;
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for (int i = 0; i < 2; i++)
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for (int j = 0; j < 3; j++)
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f[i][j] = (i + 1) * (j + 1) * inp[i][j];
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endfunction
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byte arr [2][3];
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byte res [2][3];
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assign flat =
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{ res[1][2], res[1][1], res[1][0]
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, res[0][2], res[0][1], res[0][0] };
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initial
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{ arr[1][2], arr[1][1], arr[1][0]
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, arr[0][2], arr[0][1], arr[0][0] } = 0;
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always @(posedge clk) begin
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arr[row][col] += 1;
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res = f(arr);
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end
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endmodule
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