mirror of https://github.com/zachjs/sv2v.git
27 lines
806 B
Verilog
27 lines
806 B
Verilog
module top;
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integer _sv2v_elaboration_fatal = -1;
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initial $display("Elaboration Info:");
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initial $display("Elaboration Info: ", "%b", 1);
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initial $display("Elaboration Warning:");
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initial $display("Elaboration Warning: ", "%b", 2);
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initial $display("Elaboration Error:");
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initial $display("Elaboration Error: ", "%b", 3);
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initial begin
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$display("Elaboration Fatal:");
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_sv2v_elaboration_fatal = 0;
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end
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initial begin
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$display("Elaboration Fatal:");
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_sv2v_elaboration_fatal = 0;
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end
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initial begin
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$display("Elaboration Fatal: ", "%b", 4);
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_sv2v_elaboration_fatal = 0;
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end
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initial begin
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#0;
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if (_sv2v_elaboration_fatal != -1)
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$finish(_sv2v_elaboration_fatal);
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end
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endmodule
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