mirror of https://github.com/zachjs/sv2v.git
60 lines
998 B
Verilog
60 lines
998 B
Verilog
module top;
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integer i;
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reg signed [7:0] b;
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reg signed [15:0] s;
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initial begin
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$monitor("%2d %b %b %b", $time, i, b, s);
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#1;
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s = 0;
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b = 0;
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i = 0;
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#1 i = 1;
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#1;
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b = b + 1;
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i = {1'bx, b - 8'b1, 1'bx};
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#1;
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b = b - 1;
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i = {1'bx, b + 8'b1, 1'bx};
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#1;
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b = b + 1;
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i = {1'bx, b, 1'bx};
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#1;
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b = b - 1;
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i = {1'bx, b, 1'bx};
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#1;
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i = 3;
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i = i - 1;
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s = s + 1;
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#10;
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b = b - 1;
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#1;
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i = i - 1;
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b = b + 1;
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#3;
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i = i - 1;
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#1;
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i = i + 1;
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s = s - 1;
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i[i] = s;
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b = b + 1;
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s = s - 1;
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while (b - 1 - 10 != s + 1) begin
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#1;
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if (!(i & 1))
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#10;
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i = i + 1;
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i[i] = i[i] + 1;
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b = b + 1;
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s = s - 1;
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end
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end
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endmodule
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