mirror of https://github.com/zachjs/sv2v.git
39 lines
813 B
Systemverilog
39 lines
813 B
Systemverilog
module top;
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integer i;
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byte b;
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shortint s;
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initial begin
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$monitor("%2d %b %b %b", $time, i, b, s);
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#1 i = (b = (s = 0));
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#1 i = 1;
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#1 i = {1'bx, b++, 1'bx};
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#1 i = {1'bx, b--, 1'bx};
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#1 i = {1'bx, ++b, 1'bx};
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#1 i = {1'bx, --b, 1'bx};
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#1 i = 3;
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while (--i) begin
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if (i == 2) begin
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s++;
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#10;
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end
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else if (i == 1) begin
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b++;
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#3 continue;
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$display("UNREACHABLE");
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end
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b--;
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#1;
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end
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#1;
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for (i[i++] = s--; b++ - 10 != s--; i[++i]++) begin
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#1;
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if (i & 1)
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continue;
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#10;
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end
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end
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endmodule
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