mirror of https://github.com/zachjs/sv2v.git
47 lines
1.1 KiB
Systemverilog
47 lines
1.1 KiB
Systemverilog
module mod(
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input wire [3:0] idx,
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input wire [14:0] data
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);
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localparam Y = 2;
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localparam X = 10000;
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reg start;
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`define TEST(expr, trigger, extra) \
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if (1) begin \
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function automatic f; \
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input reg ignored; \
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localparam X = Y + 1; \
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localparam THREE = X; \
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f = expr; \
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endfunction \
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`ALWAYS(trigger) begin : blk \
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localparam ZERO = 0; \
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$display(`"%2d %b expr trigger`", \
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$time, f(ZERO) extra); \
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end \
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end
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`define TEST_SIMPLE(expr) `TEST(expr, expr, )
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`TEST_SIMPLE(data)
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`TEST_SIMPLE(data[1])
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`TEST_SIMPLE(data[4])
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`TEST_SIMPLE(data[4:1])
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`TEST_SIMPLE(data[10:1])
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localparam ONE = 1;
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parameter FOUR = 4;
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`TEST_SIMPLE(data[ONE])
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`TEST_SIMPLE(data[FOUR])
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`TEST_SIMPLE(data[FOUR:ONE])
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`TEST(data[idx], data or idx, )
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`TEST(data[idx+:2], data or idx, )
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`TEST(data[THREE], data[3], )
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`TEST(data[ignored], data, )
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`TEST(data[THREE], data[0] or data[3], & data[0])
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initial start = 0;
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endmodule
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