mirror of https://github.com/zachjs/sv2v.git
24 lines
357 B
Systemverilog
24 lines
357 B
Systemverilog
`default_nettype none
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package P;
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localparam A = 4;
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localparam B = 5;
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endpackage
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`default_nettype wire
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module top;
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if (1) logic [P::A-1:0] w;
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assign x = 0;
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case (1)
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1:
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for (genvar i = 0; i < 1; i++)
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assign y = $bits(genblk1.w);
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endcase
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assign z = y;
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endmodule
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module extra;
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assign a = 0;
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endmodule
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