mirror of https://github.com/zachjs/sv2v.git
32 lines
584 B
Systemverilog
32 lines
584 B
Systemverilog
module top;
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reg a, b, c, d;
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initial begin
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fork
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#1 a = 1;
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wait(a);
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join
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$display("a %0d", $time);
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end
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initial begin
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fork
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b = 1;
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#1 wait(b);
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join
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$display("b %0d", $time);
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end
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initial begin
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fork
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#1 wait(c) $display("c done %0d", $time);
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#1 wait(d) $display("d done %0d", $time);
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begin
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#1 c = 1;
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#1 d = 1;
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end
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join
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$display("cd %0d", $time);
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end
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endmodule
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