mirror of https://github.com/zachjs/sv2v.git
20 lines
417 B
Systemverilog
20 lines
417 B
Systemverilog
module top;
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reg [1:0] a, b;
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wire [1:0] c, d;
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initial begin
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$monitor("%2d %b %b %b %b", $time, a, b, c, d);
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#1 force c = 1;
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#1 release c;
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#1 force c = b;
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#1 force d = a;
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#1 release c;
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#1 assign a = 1;
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#1 assign a = 3;
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#1 assign b = 2;
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#1 a = 0;
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#1 deassign a;
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#1 a = 0;
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#1 release d;
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end
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endmodule
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