mirror of https://github.com/zachjs/sv2v.git
18 lines
384 B
Systemverilog
18 lines
384 B
Systemverilog
module top;
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wire [3:0] a, b, w, x, y, z;
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assign a = 4'b1111;
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assign b = 4'b0001;
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// loses upper bit
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assign w = (a + b) >> 1;
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// preserves upper bit via implicit extension
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assign y = (0 + a + b) >> 1;
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assign y = (a + b + 0) >> 1;
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// preserves upper bit via "casting"
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wire [4:0] tmp;
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assign tmp = x + b;
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assign z = tmp >> 1;
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endmodule
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