mirror of https://github.com/zachjs/sv2v.git
21 lines
403 B
Systemverilog
21 lines
403 B
Systemverilog
package P;
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function automatic logic [7:0] f(input logic [2:0] p);
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logic [7:0] r;
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r = '0;
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r[p+:2] = '1;
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return r;
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endfunction
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endpackage
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module top;
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logic [2:0] p;
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logic [7:0] q;
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assign q = P::f(p);
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initial begin
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$monitor("%0d, p=%b q=%b", $time, p, q);
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#1 p = 0;
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while (p != 7)
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#1 p = p + 1;
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end
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endmodule
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