mirror of https://github.com/zachjs/sv2v.git
88 lines
2.1 KiB
Verilog
88 lines
2.1 KiB
Verilog
// Ignored the compiler directive
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module Device(
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input wire [7:0] dataIn,
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output wire [31:0] dataOut,
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input wire clock, clear
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);
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// Expanded interface declaration
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wire theInterface_clock;
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wire theInterface_clear;
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wire [31:0] theInterface_data;
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wire theInterface_shift;
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// Interface instantiation
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assign theInterface_clock = clock;
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assign theInterface_clear = clear;
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Producer producer(
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// Expanded interface
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.myInterface_clock(theInterface_clock),
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.myInterface_clear(theInterface_clear),
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.myInterface_data(theInterface_data),
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.myInterface_shift(theInterface_shift),
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.dataIn(dataIn)
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);
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Consumer consumer(
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// Expanded interface
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.myInterface_clock(theInterface_clock),
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.myInterface_clear(theInterface_clear),
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.myInterface_data(theInterface_data),
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.myInterface_shift(theInterface_shift),
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.dataOut(dataOut)
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);
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endmodule
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module Producer(
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// Port direction from SimpleInterface.Producer modport
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input wire myInterface_clock,
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input wire myInterface_clear,
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output wire [31:0] myInterface_data,
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input wire myInterface_shift,
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input wire [7:0] dataIn
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);
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reg [31:0] inProgress;
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always @(posedge myInterface_clock) begin
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if(myInterface_clear) begin
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inProgress <= 32'b0;
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end else if(myInterface_shift) begin
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inProgress <= {inProgress[23:0], dataIn};
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end
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end
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assign myInterface_data = inProgress;
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endmodule
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module Consumer(
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// Port direction from SimpleInterface.Consumer modport
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input wire myInterface_clock,
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input wire myInterface_clear,
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input wire [31:0] myInterface_data,
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output reg myInterface_shift,
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output wire [31:0] dataOut
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);
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// Just want this variable to make the test bench nicer
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wire local_shift;
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assign local_shift = myInterface_shift;
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always @(posedge myInterface_clock)
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if(myInterface_clear) begin
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myInterface_shift <= 1'b0;
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end else begin
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myInterface_shift <= ~myInterface_shift;
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end
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assign dataOut = myInterface_data;
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endmodule |