mirror of https://github.com/zachjs/sv2v.git
31 lines
650 B
Verilog
31 lines
650 B
Verilog
`default_nettype none
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module top;
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reg [31:0] data;
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wire parity;
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Device dut(
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.data(data),
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.parity(parity)
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);
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initial begin
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$monitor($time, " data: %h parity: %b", data, parity);
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data = 32'b0;
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#10 data = 32'h00000003;
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#10 data = 32'h00000300;
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#10 data = 32'h00030000;
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#10 data = 32'h03000000;
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#10 data = 32'h01010101;
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#10 data = 32'h01000101;
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#10 data = 32'h00010101;
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#10 data = 32'h01010001;
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#10 data = 32'h01010100;
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#10 data = 32'hffffffff;
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#10 data = 32'hfeffffff;
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#10 $finish;
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end
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endmodule
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