mirror of https://github.com/zachjs/sv2v.git
38 lines
734 B
Verilog
38 lines
734 B
Verilog
`default_nettype none
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module top;
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reg clock, clear;
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reg [7:0] dataIn;
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wire check1, check2;
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wire [63:0] checkData;
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Example dut(
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.clock(clock),
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.clear(clear),
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.dataIn(dataIn),
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.check1(check1),
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.check2(check2),
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.checkData(checkData)
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);
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initial begin
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clock = 1;
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forever #5 clock = ~clock;
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end
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initial begin
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$monitor($time, " data: %h check: %b checkData: %h", dataIn, {check1, check2}, checkData);
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clear = 1'b1;
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dataIn = 8'h0;
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repeat(3) @(posedge clock);
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clear = 1'b0;
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@(posedge clock);
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dataIn = 8'haa;
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repeat(20) @(posedge clock);
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$finish;
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end
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endmodule
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