mirror of https://github.com/zachjs/sv2v.git
23 lines
391 B
Verilog
23 lines
391 B
Verilog
`default_nettype none
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module top;
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reg rawMode;
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wire [1:0] rawOperation;
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Example dut(
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.rawMode(rawMode),
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.rawOperation(rawOperation)
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);
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initial begin
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$monitor($time, " rawMode: %b rawOperation: %b", rawMode, rawOperation);
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rawMode = 1'b0;
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#10 rawMode = 1'b1;
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#10 rawMode = 1'b0;
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#10 $finish;
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end
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endmodule
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