mirror of https://github.com/zachjs/sv2v.git
69 lines
1.4 KiB
Verilog
69 lines
1.4 KiB
Verilog
`default_nettype none
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module Example(
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input wire [1:0] select,
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// This is an array of 3 (4-bit wide) elements
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output wire [11:0] data
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);
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// Unflatten the array
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wire [3:0] __data[2:0];
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assign data = {__data[2], __data[1], __data[0]};
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UniqueCase case0(.select(select), .data(__data[0]));
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WildcardCase case1(.select(select), .data(__data[1]));
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DefaultCase case2(.select(select), .data(__data[2]));
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endmodule
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module UniqueCase(
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input wire [1:0] select,
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output reg [3:0] data
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);
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always @* begin
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data = 4'b0;
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// Unique keyword doesn't exist in Verilog
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case(select)
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2'd0: data = 4'ha;
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2'd1: data = 4'h6;
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2'd2: data = 4'h3;
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endcase
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end
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endmodule
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module WildcardCase(
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input wire [1:0] select,
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output reg [3:0] data
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);
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always @* begin
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data = 4'b0;
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// Unique keyword doesn't exist in Verilog
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// casez doesn't exist in VTR, so manually elaborating it
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case(select) // casez
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2'b00: data = 4'h3;
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// 2'b1?: data = 4'hd;
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2'b10: data = 4'hd;
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2'b11: data = 4'hd;
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endcase
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end
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endmodule
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module DefaultCase(
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input wire [1:0] select,
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output reg [3:0] data
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);
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always @* begin
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data = 4'b0;
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case (select)
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2'b00: data = 4'h7;
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2'b01: data = 4'h9;
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default: data = 4'h8;
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endcase
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end
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endmodule
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