mirror of https://github.com/zachjs/sv2v.git
21 lines
553 B
Verilog
21 lines
553 B
Verilog
module top;
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generate
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if (1) begin : intf
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wire x;
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end
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endgenerate
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wire y;
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genvar i, j, k;
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generate
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for (i = 2; i >= 0; i = i - 1) begin
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initial $display("ModuleA %b %b", intf.x, y);
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for (j = 2; j >= 0; j = j - 1) begin
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initial $display("ModuleB %b %b", intf.x, y);
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for (k = 2; k >= 0; k = k - 1) begin
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initial $display("ModuleC %b %b", intf.x, y);
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end
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end
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end
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endgenerate
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endmodule
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