mirror of https://github.com/zachjs/sv2v.git
23 lines
459 B
Verilog
23 lines
459 B
Verilog
module top;
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initial begin
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$write("[%0t] Info: ", $time);
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$display;
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$write("[%0t] Info: ", $time);
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$display("%b", 1);
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$write("[%0t] Warning: ", $time);
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$display;
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$write("[%0t] Warning: ", $time);
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$display("%b", 2);
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$write("[%0t] Error: ", $time);
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$display;
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$write("[%0t] Error: ", $time);
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$display("%b", 3);
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$write("[%0t] Fatal: ", $time);
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$display;
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$finish;
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$write("Fatal:");
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$display("%b", 4);
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$finish(0);
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end
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endmodule
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