mirror of https://github.com/zachjs/sv2v.git
d4284163dc
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|---|---|---|
| .. | ||
| README.md | ||
| alu.sv | ||
| alu.v | ||
| alu_tb.v | ||
| array.sv | ||
| array.v | ||
| array_tb.v | ||
| cache_request.sv | ||
| cache_request.v | ||
| cache_request_tb.v | ||
| case.sv | ||
| case.v | ||
| case_tb.v | ||
| complex_interface.sv | ||
| complex_interface.v | ||
| complex_interface_tb.v | ||
| double_clock.sv | ||
| double_clock.v | ||
| double_clock_tb.v | ||
| enum.sv | ||
| enum.v | ||
| enum_tb.v | ||
| fsm.sv | ||
| fsm.v | ||
| fsm_tb.v | ||
| functions.sv | ||
| functions.v | ||
| functions_tb.v | ||
| inline_concat.sv | ||
| inline_concat.v | ||
| inline_concat_tb.v | ||
| port_connections.sv | ||
| port_connections.v | ||
| port_connections_tb.v | ||
| run.sh | ||
| simple_interface.sv | ||
| simple_interface.v | ||
| simple_interface_tb.v | ||
| split_ports.sv | ||
| split_ports.v | ||
| split_ports_tb.v | ||
| struct.sv | ||
| struct.v | ||
| struct_tb.v | ||
| typedef.sv | ||
| typedef.v | ||
| typedef_tb.v | ||
README.md
relong Tests
These tests are borrowed from Reid Long's HDL Examples repository. That repository was intended to provide examples for how the conversions in this project could be done.
Each test case (say, "foo") is comprised of the following files:
foo.sv: original SystemVerilogfoo.v: hand-converted Verilogfoo_tb.v: basic testbench exercising the given modules
The SystemVerilog source file is converted to Verilog using sv2v, and then both the converted file and the reference Verilog are simulated using Icarus Verilog. This produces VCD files for each which are expected to match exactly, except for the timestamp.
Modifications
The following differences exist between the tests in this folder and their corresponding versions in the source repository.
- The
inline_concatfiles were modified to remove a stray trailing semicolon. Though some tools allow for stray semicolons,iverilogdoes not. array.vpreviously had a custom implementation of$clog2, which was removed.cache_request.svwas modified to include a plain decimal literal to ensure coverage beyond the unbased-unsized literals.- The
cache_request2test is omitted. It was only an example for debugging a VCS-specific issue encountered withcache_request.