mirror of https://github.com/zachjs/sv2v.git
48 lines
1.0 KiB
Plaintext
48 lines
1.0 KiB
Plaintext
name: verilog
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version: 0.0.12
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category: Language, Hardware, Embedded
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synopsis: Verilog preprocessor, parser, and AST.
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description:
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A parser and supporting a small subset of Verilog.
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Intended for machine generated, synthesizable code.
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author: Tom Hawkins <tomahawkins@gmail.com>
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maintainer: Tom Hawkins <tomahawkins@gmail.com>
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license: BSD3
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license-file: LICENSE
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homepage: http://github.com/tomahawkins/verilog
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build-type: Simple
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cabal-version: >= 1.10
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library
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default-language: Haskell2010
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build-tools:
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alex >= 3 && < 4,
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happy >= 1 && < 2
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build-depends:
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base >= 4.8.2.0 && < 5.0,
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array >= 0.5.1.0 && < 0.6
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exposed-modules:
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Data.BitVec
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Language.Verilog
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Language.Verilog.AST
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Language.Verilog.Parser
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Language.Verilog.Parser.Lex
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Language.Verilog.Parser.Parse
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Language.Verilog.Parser.Preprocess
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Language.Verilog.Parser.Tokens
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ghc-options: -W
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source-repository head
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type: git
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location: git://github.com/tomahawkins/verilog.git
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