mirror of https://github.com/zachjs/sv2v.git
37 lines
877 B
Verilog
37 lines
877 B
Verilog
module Producer(clock, data);
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parameter INIT = 0;
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input clock;
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output reg [54:0] data;
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initial data[11*4] = INIT;
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always @(clock) begin : block_name
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integer i, j;
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for (i = 4; i >= 0; i--) begin
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for (j = 9; j >= 0; j--) begin
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data[11*(4-i) + j + 1] = data[11*(4-i) + j];
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end
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if (i != 0)
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data[11*(4-i) + 0] = data[11*(4-(i-1)) + 10];
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end
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data[11*4] = ~data[11*4];
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end
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endmodule
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module top;
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reg clock;
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initial begin
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clock = 1;
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repeat (100)
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#1 clock = ~clock;
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end
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wire [54:0] foo;
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Producer #(.INIT(0)) p1(clock, foo);
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wire [109:0] bar;
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Producer #(.INIT(0)) p2(clock, bar[54:0]);
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Producer #(.INIT(1)) p3(clock, bar[109:55]);
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initial
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$monitor("%d %b %b", $time, foo, bar);
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endmodule
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