mirror of https://github.com/zachjs/sv2v.git
41 lines
1.0 KiB
Systemverilog
41 lines
1.0 KiB
Systemverilog
module Producer(clock, data);
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parameter INIT = 0;
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input logic clock;
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output logic [10:0] data [5];
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initial data[0][0] = INIT;
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always @(clock) begin
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integer i, j;
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for (i = 4; i >= 0; i--) begin
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for (j = 9; j >= 0; j--) begin
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data[i][j + 1] = data[i][j];
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end
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if (i != 0)
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data[i][0] = data[i-1][10];
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end
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data[0][0] = ~data[0][0];
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end
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endmodule
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module top;
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reg clock;
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initial begin
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clock = 1;
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repeat (100)
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#1 clock = ~clock;
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end
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logic [10:0] foo [5];
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Producer #(.INIT(0)) p1(clock, foo);
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logic [10:0] bar [10];
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Producer #(.INIT(0)) p2(clock, bar[0:4]);
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Producer #(.INIT(1)) p3(clock, bar[5:9]);
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initial
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$monitor("%d %b%b%b%b%b %b%b%b%b%b%b%b%b%b%b", $time,
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foo[0], foo[1], foo[2], foo[3], foo[4],
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bar[0], bar[1], bar[2], bar[3], bar[4],
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bar[5], bar[6], bar[7], bar[8], bar[9]
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);
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endmodule
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