mirror of https://github.com/zachjs/sv2v.git
51 lines
1.0 KiB
Verilog
51 lines
1.0 KiB
Verilog
module top;
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reg [1:0] select;
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wire [3:0] data [2:0];
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UniqueCase case0(.select(select), .data(data[0]));
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Unique0Case case1(.select(select), .data(data[1]));
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PriorityCase case2(.select(select), .data(data[2]));
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initial begin end
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endmodule
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module UniqueCase(
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input [1:0] select,
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output reg [3:0] data
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);
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always @* begin
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data = 4'b0;
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case(select)
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2'd0: data = 4'ha;
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2'd1: data = 4'h6;
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2'd2: data = 4'h3;
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endcase
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end
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endmodule
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module Unique0Case(
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input [1:0] select,
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output reg [3:0] data
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);
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always @* begin
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data = 4'b0;
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case(select)
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2'd0: data = 4'ha;
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2'd1: data = 4'h6;
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2'd2: data = 4'h3;
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endcase
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end
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endmodule
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module PriorityCase(
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input [1:0] select,
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output reg [3:0] data
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);
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always @* begin
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data = 4'b0;
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case(select)
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2'd0: data = 4'ha;
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2'd1: data = 4'h6;
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2'd2: data = 4'h3;
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endcase
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end
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endmodule
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