mirror of https://github.com/zachjs/sv2v.git
23 lines
519 B
Systemverilog
23 lines
519 B
Systemverilog
module example(
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input wire inp [7:0],
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output wire out [7:0]
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);
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for (genvar i = 0; i < 8; ++i)
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assign out[i] = ~inp[i];
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endmodule
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module top;
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reg arr1 [1:0][7:0];
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reg arr2 [1:0][1:0][7:0];
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wire out1 [7:0];
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wire out2 [7:0];
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example e1(arr1[0], out1);
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example e2(arr2[0][0], out2);
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initial begin
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for (integer i = 0; i < 8; ++i) begin
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#1 arr1[0][i] = (8'hAD >> i) & 1'b1;
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#1 arr2[0][0][i] = (8'h42 >> i) & 1'b1;
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end
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end
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endmodule
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