mirror of https://github.com/zachjs/sv2v.git
12 lines
377 B
Verilog
12 lines
377 B
Verilog
module top;
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`include "multipack_prec.vh"
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assign arr2[0][0] = arr1[0][0];
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assign arr2[0][1] = arr1[0][1];
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assign arr2[0][3:2] = arr1[0][3:2];
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// ideally we'd use the original as the reference, but the slices in the
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// original fail due to steveicarus/iverilog#97
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assign arr2[1][1:0] = arr1[1][1:0];
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assign arr2[1][3:2] = arr1[1][3:2];
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endmodule
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