mirror of https://github.com/zachjs/sv2v.git
19 lines
463 B
Systemverilog
19 lines
463 B
Systemverilog
module Module(input clock, input clear, input data);
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logic x, y;
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assign y = data;
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assign x = y;
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assert property (
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@(posedge clock) disable iff(clear) x == y
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);
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named: assert property (
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@(posedge clock) disable iff(clear) x == y
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);
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task hello;
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$display("Hello!");
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endtask
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always @(posedge clock) begin
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assert property (x == y);
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named_stmt: assert property (x == y);
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end
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endmodule
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