mirror of https://github.com/zachjs/sv2v.git
56 lines
1.8 KiB
Systemverilog
56 lines
1.8 KiB
Systemverilog
// This test was adapted from Section 27.6 of IEEE 1800-2017
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module mod;
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initial $dumpvars(0, mod);
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// needed because of steveicarus/iverilog#528
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`ifdef __ICARUS__
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`define BEGIN(name) begin : name
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`define END end
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`else
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`define BEGIN(name)
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`define END
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`endif
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parameter genblk2 = 0;
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genvar i;
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// The following generate block is implicitly named genblk1
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if (genblk2) `BEGIN(genblk1) logic a; `END // mod.genblk1.a
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else `BEGIN(genblk1) logic b; `END // mod.genblk1.b
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// The following generate block is implicitly named genblk02
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// as genblk2 is already a declared identifier
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if (genblk2) `BEGIN(genblk02) logic a; `END // mod.genblk02.a
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else `BEGIN(genblk02) logic b; `END // mod.genblk02.b
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// The following generate block would have been named genblk3
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// but is explicitly named g1
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for (i = 0; i < 1; i = i + 1) begin : g1 // block name
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// The following generate block is implicitly named genblk1
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// as the first nested scope inside g1
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if (1) `BEGIN(genblk1) logic a; `END // mod.g1[0].genblk1.a
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end
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// The following generate block is implicitly named genblk4 since
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// it belongs to the fourth generate construct in scope "mod".
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// The previous generate block would have been
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// named genblk3 if it had not been explicitly named g1
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for (i = 0; i < 1; i = i + 1) `BEGIN(genblk4)
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// The following generate block is implicitly named genblk1
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// as the first nested generate block in genblk4
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if (1) `BEGIN(genblk1) logic a; `END // mod.genblk4[0].genblk1.a
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`END
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// The following generate block is implicitly named genblk5
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if (1) `BEGIN(genblk5) logic a; `END // mod.genblk5.a
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endmodule
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module top;
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mod #(0) m0();
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mod #(1) m1();
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endmodule
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