mirror of https://github.com/zachjs/sv2v.git
73 lines
2.1 KiB
Systemverilog
73 lines
2.1 KiB
Systemverilog
module top;
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// Derived from: https://www.amiq.com/consulting/2017/05/29/how-to-pack-data-using-systemverilog-streaming-operators/
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typedef struct packed {
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logic [3:0] addr;
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logic [3:0] data;
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} packet_t;
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initial begin
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// TODO: Add support for implicitly sized arrays.
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logic [1:0] array[4] = '{ 2'b10, 2'b01, 2'b11, 2'b00 };
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packet_t packet = {<<4{ {<<2{array}} }};
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$display("packet addr = %b", packet.addr);
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$display("packet data = %b", packet.data);
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end
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initial begin
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logic [23:0] temp;
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temp = {>>byte{24'h060708}};
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$display("%h", temp);
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temp = {<<byte{24'h060708}};
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$display("%h", temp);
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temp = {>>bit{24'h060708}};
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$display("%h", temp);
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temp = {<<bit{24'h060708}};
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$display("%h", temp);
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temp = {>>7{24'h060708}};
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$display("%h", temp);
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temp = {<<7{24'h060708}};
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$display("%h", temp);
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temp = {>>7{20'h60708}};
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$display("%h", temp);
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// TODO: Handle this edge case.
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//temp = {<<7{20'h60708}};
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//$display("%h", temp);
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temp = {>>7{16'h0708}};
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$display("%h", temp);
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temp = {<<7{16'h0708}};
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$display("%h", temp);
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end
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task test_unpack;
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input logic [23:0] in;
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logic [0:0] i;
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logic [1:0] j;
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logic [2:0] k;
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logic [5:0] l;
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logic [11:0] m;
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{>>byte{i, j, k, l, m}} = in;
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$display("%b %b %b %b %b", i, j, k, l, m);
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{<<byte{i, j, k, l, m}} = in;
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$display("%b %b %b %b %b", i, j, k, l, m);
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{>>bit{i, j, k, l, m}} = in;
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$display("%b %b %b %b %b", i, j, k, l, m);
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{<<bit{i, j, k, l, m}} = in;
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$display("%b %b %b %b %b", i, j, k, l, m);
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{>>7{i, j, k, l, m}} = in;
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$display("%b %b %b %b %b", i, j, k, l, m);
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{<<7{i, j, k, l, m}} = in;
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$display("%b %b %b %b %b", i, j, k, l, m);
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endtask
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initial begin
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test_unpack(24'h060708);
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test_unpack(24'hC02375);
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test_unpack(24'h12E3B8);
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end
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endmodule
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