mirror of https://github.com/zachjs/sv2v.git
101 lines
2.7 KiB
Systemverilog
101 lines
2.7 KiB
Systemverilog
module m_def #(
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parameter type T = logic
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);
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T x = 0;
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initial begin
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$display("m_def %b %b %d", x, x+1, $bits(T));
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end
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endmodule
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module m_nodef #(
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parameter type T
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);
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T x = 0;
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initial begin
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$display("m_nodef %b %b %d", x, x+1, $bits(T));
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end
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endmodule
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module n_nodef #(
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parameter type T,
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parameter type U
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);
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T x = 0;
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U y = 1;
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initial begin
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$display("n_nodef %b %b %d", x, x+1, $bits(T));
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$display("n_nodef %b %b %d", y, y+1, $bits(U));
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end
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endmodule
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module n_def #(
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parameter type T = logic,
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parameter type U = logic
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);
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T x = 0;
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U y = 1;
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initial begin
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$display("n_def %b %b %d", x, x+1, $bits(T));
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$display("n_def %b %b %d", y, y+1, $bits(U));
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end
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endmodule
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module n_tdef #(
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parameter type T,
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parameter type U = logic
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);
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T x = 0;
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U y = 1;
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initial begin
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$display("n_tdef %b %b %d", x, x+1, $bits(T));
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$display("n_tdef %b %b %d", y, y+1, $bits(U));
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end
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endmodule
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// TODO Add support for parameters without default values.
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module o_nodef #(
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parameter a = 0,
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parameter type T,
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parameter type U,
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parameter b = 0
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);
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T x = a;
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U y = b;
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initial begin
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$display("n_nodef a=%d %b %b %d", a, x, x+1, $bits(T));
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$display("n_nodef b=%d %b %b %d", b, y, y+1, $bits(U));
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end
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endmodule
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module top; endmodule
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// Top level modules appear to be generally instantiated in lexicographic order,
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// but instances within a module do not. This silliness helps produce more
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// consistent output.
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module a_1; m_def x(); endmodule
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module a_2; m_def #(logic [1:0]) x(); endmodule
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module a_3; m_def #(.T(logic [1:0])) x(); endmodule
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module b_1; m_nodef #(logic [1:0]) x(); endmodule
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module b_2; m_nodef #(.T(logic [1:0])) x(); endmodule
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module c_1; n_nodef #(logic [1:0], logic [2:0]) x(); endmodule
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module c_2; n_nodef #(.T(logic [1:0]), .U(logic)) x(); endmodule
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module c_3; n_nodef #(.U(logic), .T(logic [1:0])) x(); endmodule
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module d_1; n_def #(logic [1:0], logic [2:0]) x(); endmodule
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module d_2; n_def #(.T(logic [1:0])) x(); endmodule
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module d_3; n_def #(.U(logic [1:0])) x(); endmodule
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module d_4; n_def #(.U(logic), .T(logic [1:0])) x(); endmodule
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module d_5; n_def x(); endmodule
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module e_1; n_tdef #(logic [1:0], logic [2:0]) x(); endmodule
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module e_2; n_tdef #(.T(logic [1:0]), .U(logic)) x(); endmodule
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module e_3; n_tdef #(.U(logic), .T(logic [1:0])) x(); endmodule
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module f_1; o_nodef #(1, logic [1:0], logic [2:0], 0) x(); endmodule
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module f_2; o_nodef #(.T(logic [1:0]), .U(logic), .b(1), .a(0)) x(); endmodule
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module f_3; o_nodef #(0, logic [1:0], logic [2:0], 1) x(); endmodule
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module f_4; o_nodef #(.T(logic [1:0]), .U(logic), .b(0), .a(1)) x(); endmodule
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