mirror of https://github.com/zachjs/sv2v.git
59 lines
1.0 KiB
Verilog
59 lines
1.0 KiB
Verilog
`define PRINT(name, val) \
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dummy``name = val; \
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$display("%h %h %0d %0d", \
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val, dummy``name, $bits(val), $bits(dummy``name));
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`define PRINT_UNSIZED(name, val) \
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dummy``name = val; \
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$display("%h %h %0d", \
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val, dummy``name, $bits(dummy``name));
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module top;
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reg [31:0] dummyA;
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reg [31:0] dummyB;
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reg [31:0] dummyC;
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reg [31:0] dummyD;
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reg [31:0] dummyE;
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reg [0:0] dummyF;
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reg [0:0] dummyG;
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reg [3:0] dummyH;
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initial begin
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`PRINT(A, 0)
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`PRINT(A, 1)
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`PRINT(A, 2)
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`PRINT(B, 2)
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`PRINT(B, 1)
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`PRINT(B, 3)
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`PRINT(C, 20)
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`PRINT(C, 0)
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`PRINT(C, 19)
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`PRINT(D, 16)
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`PRINT(D, 17)
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`PRINT(D, 18)
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`PRINT(E, 0)
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`PRINT(E, 16)
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`PRINT(E, 17)
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`PRINT(E, 18)
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`PRINT(E, 2)
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`PRINT(E, 3)
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`PRINT(F, 1'b0)
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`PRINT(F, 1'b1)
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`PRINT(G, 1'b0)
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`PRINT(G, 1'b1)
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`PRINT_UNSIZED(H, 'b1)
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`PRINT_UNSIZED(H, 'b0)
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end
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endmodule
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