mirror of https://github.com/zachjs/sv2v.git
23 lines
473 B
Systemverilog
23 lines
473 B
Systemverilog
module top;
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function f;
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input x;
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f = 1'b1 ^ x;
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$display("f(%b) called", x);
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endfunction
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task t;
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input x;
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$display("t(%b) called", x);
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endtask
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initial begin
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type(f(0)) x = f(0);
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$display("%b", x);
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$display("%b", $bits(x));
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$display("%b", $bits(type(x)));
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$display("%b", $bits(logic [0:1+$bits(type(x))]));
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f(1);
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void'(f(0));
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t(1);
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end
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endmodule
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