mirror of https://github.com/zachjs/sv2v.git
76 lines
1.6 KiB
Systemverilog
76 lines
1.6 KiB
Systemverilog
module top;
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wire [0:31] a;
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for (genvar n = 0; n < 32; n++) begin : gen_filter
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assign a[n] = n & 1;
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wire x;
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assign x = a[n];
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end
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wire [0:31] b;
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for (genvar n = 0; n < 32; n++) begin : gen_filter_other
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assign b[n] = ~gen_filter[n].x;
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end
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initial
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for (integer i = 0; i < 32; i++)
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$display("1: ", a[i]);
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integer i = 0;
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initial
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for (; i < 32; i++)
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$display("2: ", ~a[i]);
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initial begin
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for (integer i = 0, j = 42; i < 32; i++)
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$display("3: ", ~a[i] + 5, " j=", j);
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end
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initial begin
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integer i, j;
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for (i = 0, j = 97; i < 32; i++)
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$display("4: ", ~a[i] + 10, " j=", j);
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end
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integer j = 0, k;
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initial begin
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for (; j < 4; j++) begin
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k = 0;
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for (; k < 8; k++)
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$display("5: ", ~a[j * 8 + k] + 11);
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end
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end
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initial begin
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integer i = 0;
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for (; i < 32; i++)
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$display("6: ", ~a[i]);
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end
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initial begin
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integer j = 0, k;
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for (; j < 4; j++) begin
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k = 0;
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for (; k < 8; k++)
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$display("7: ", ~a[j * 8 + k] + 11);
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end
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end
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initial
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for (integer i = 0; i < 32; i++)
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$display("8: ", a[i], b[i]);
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logic start;
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assign start = gen_filter[0].x;
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initial $display(start);
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logic [0:31] c;
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generate
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;
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for (genvar n = 0; n < 32; n = n + 1)
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assign c[n] = n & 1;
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for (genvar m = 0; m < 32; m = m + 1) begin end
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endgenerate
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endmodule
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