mirror of https://github.com/zachjs/sv2v.git
17 lines
458 B
Systemverilog
17 lines
458 B
Systemverilog
module top;
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wire (supply0, supply1) a = 1;
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wire (strong1, strong0) b = 1;
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wire (pull0, highz1) c = 1;
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wire (pull1, highz0) d = 1;
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wire (highz0, weak1) e = 1;
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wire (highz1, weak0) f = 1;
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wire u, v, w, x, y, z;
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assign (supply0, supply1) u = 1;
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assign (strong1, strong0) v = 1;
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assign (pull0, highz1) w = 1;
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assign (pull1, highz0) x = 1;
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assign (highz0, weak1) y = 1;
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assign (highz1, weak0) z = 1;
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endmodule
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