mirror of https://github.com/zachjs/sv2v.git
12 lines
380 B
Systemverilog
12 lines
380 B
Systemverilog
module top; endmodule
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`define MODULE(str) module str; initial $display(`"hello str`"); endmodule
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`define MACRO_A(inv, str) `inv(str)
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`define MACRO_B(inv, str) ```inv(str)
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`define MACRO_C(inv1, inv2, str) `inv1``inv2(str)
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`MODULE(example1)
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`MACRO_A(MODULE, example2)
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`MACRO_B(MODULE, example3)
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`MACRO_C(MOD, ULE, example4)
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`MACRO_C(M, ODULE, example5)
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`MACRO_C(, MODULE, example6)
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