mirror of https://github.com/zachjs/sv2v.git
17 lines
337 B
Verilog
17 lines
337 B
Verilog
`define MACRO_A(x, y) \
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initial begin \
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$display(`"x %b`", x); \
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$display(`"y %b`", y); \
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end
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`define MACRO_B(x, y, z) initial $display(x, y, z);
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module top;
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`MACRO_A(1 + 2, 1'b1 & 1)
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`MACRO_B(
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"/* not a block comment */",
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"// not a line comment",
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"cool \046 \042 ( } { beans\\"
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)
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endmodule
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