mirror of https://github.com/zachjs/sv2v.git
19 lines
500 B
Verilog
19 lines
500 B
Verilog
module top;
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initial begin
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repeat (13) $display(42);
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repeat (1) $display("foo\nbar");
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repeat (1) $display(" foo \n bar ");
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repeat (5) $display("test");
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repeat (35) $display("bar", "bar");
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repeat (35) $display("foo", "foo");
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$display("foo", 1);
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$display("foo", 1);
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$display("foo", 2);
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$display("display");
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$display("s", "foo", "ss");
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$display("s", "display", "ss");
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$display("s foo = \"foo\"");
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$display("s display = \"display\"");
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end
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endmodule
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