mirror of https://github.com/zachjs/sv2v.git
140 lines
1.8 KiB
Systemverilog
140 lines
1.8 KiB
Systemverilog
module top;
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integer x = 0;
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integer y = 1;
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`define GOOD \
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$display("%x %x %d", x, y, `__LINE__); \
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x += 1; $display(x);
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`define BAD \
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$display("FAIL line ", `__LINE__);
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initial begin
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`include "cond.vh"
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$display(`RESULT);
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`include "cond.vh"
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$display(`RESULT);
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`include "cond.vh"
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$display(`RESULT);
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`undef INCLUDED
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`include "cond.vh"
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$display(`RESULT);
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`include "cond.vh"
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$display(`RESULT);
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`define A
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`define C
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`ifdef A
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`GOOD
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`endif
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`ifndef A
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`BAD
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`endif
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`ifdef B
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`BAD
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`endif
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`ifndef B
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`GOOD
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`endif
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`ifdef A
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`GOOD
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`else
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`BAD
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`endif
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`ifdef B
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`BAD
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`define A
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`else
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`GOOD
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`endif
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`ifndef A
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`BAD
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`elsif B
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`BAD
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`elsif A
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`GOOD
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`else
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`BAD
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`endif
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`ifndef B
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`GOOD
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`elsif A
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`BAD
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`elsif B
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`BAD
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`else
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`BAD
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`endif
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`ifdef B
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`BAD
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`elsif A
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`GOOD
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`else
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`BAD
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`endif
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`ifdef B
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`BAD
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`elsif A
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`GOOD
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`elsif B
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`BAD
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`else
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`BAD
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`endif
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`ifdef B
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`BAD
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`elsif A
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`GOOD
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`elsif C
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`BAD
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`else
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`BAD
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`endif
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`ifdef A
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`ifdef B
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`BAD
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`ifdef B
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`BAD
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`else
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`BAD
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`endif
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`BAD
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`else
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`ifdef C
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`GOOD
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`ifndef C
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`BAD
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`else
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`GOOD
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`endif
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`else
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`BAD
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`endif
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`endif
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`GOOD
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`else
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`BAD
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`ifdef B
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`BAD
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`else
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`BAD
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`endif
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`BAD
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`endif
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end
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endmodule
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