mirror of https://github.com/zachjs/sv2v.git
42 lines
806 B
Verilog
42 lines
806 B
Verilog
module UniqueCase(
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input wire [1:0] select,
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output reg [3:0] data
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);
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always @* begin
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data = 4'b0;
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case (select)
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2'd0: data = 4'ha;
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2'd1: data = 4'h6;
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2'd2: data = 4'h3;
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endcase
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end
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endmodule
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module Unique0Case(
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input wire [1:0] select,
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output reg [3:0] data
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);
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always @* begin
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data = 4'b0;
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case (select)
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2'd0: data = 4'ha;
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2'd1: data = 4'h6;
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2'd2: data = 4'h3;
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endcase
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end
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endmodule
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module PriorityCase(
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input wire [1:0] select,
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output reg [3:0] data
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);
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always @* begin
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data = 4'b0;
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case (select)
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2'd0: data = 4'ha;
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2'd1: data = 4'h6;
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2'd2: data = 4'h3;
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endcase
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end
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endmodule
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